library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity addshift is
    Port ( a_in : in  STD_LOGIC_VECTOR (7 downto 0);
           b_in : in  STD_LOGIC_VECTOR (7 downto 0);
           start : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
			  ready: out std_logic;
			  p : inout std_logic_vector(15 downto 0);
			  r :  out std_logic_vector(15 downto 0)
          );
end addshift;

architecture shift_add_better_arch of addshift is 

constant WIDTH : integer :=8; 
constant C_WIDTH: integer:=4; 
signal C_INIT: unsigned(3 downto 0) :="1000"; 
type state_type is (idle, add_shft); 
signal state_reg , state_next : state_type; 
signal a_reg , a_next : unsigned(7 downto 0) ; 
signal n_reg , n_next : unsigned(3 downto 0) ; 
signal p_reg , p_next : unsigned (15 downto 0) ; 
 --- alias for the upper and lower parts of p-reg 
alias pu_next : unsigned(8 downto 0) is 
p_next(16 downto 8) ;
alias pu_reg: unsigned(8 downto 0) is 
p_reg(16 downto 8) ;
alias pl_reg: unsigned(15 downto 0) is 
p_reg(15 downto 0) ; 
begin
ready<='0';
process (clk ,reset) 
 begin 
if reset='l' then 
 state_reg <= idle; 
a_reg <= (others=>'0'); 
n_reg <= (others=>'0'); 
p_reg <= (others=>'0');
elsif (clk'event and clk='l') then 
state_reg <= state_next; 
a_reg <= a_next; 
n_reg <= n_next; 
p_reg <= p_next; 
end if; 
end process; 
process (start,state_reg,a_reg,n_reg,p_reg,a_in,b_in,n_next,p_next) 
begin 
a_next <= a_reg; 
n_next <= n_reg; 
p_next <= p_reg; 
ready <='0';
case state_reg is 
when idle =>
if start='l' then
p_next <= "000000000" & unsigned(b_in) ;
a_next <= unsigned(a_in); 
n_next <= C_INIT; 
state_next <= add_shft ;
else
state_next <= idle; 
end if; 
ready ='l'; 
when add_shft => 
n_next <= n_reg - 1; 
if (p_reg(0)='l') then 
pu_next <= pu_reg + ( '0' & a_reg); 
else 
pu_next <= pu_reg; 
end if ; 
p_next <= '0' & pu_next & 
pl_reg(7 downto 1); 
if (n_next /= "0000") then 
state_next <= add_shft ; 
else
state_next <= idle; 
end if ; 
end case; 
end process; 
 r <=  std_logic_vector(p_reg(unsigned(P)*7 downto 0)); 
end shift_add_better_arch;